# Changelog *Versions: Major.Minor.Patch* Changelogs are synchronized for Major.Minor version numbers, but each project has it's own patch version (eg: src/fpga might be version 1.1.2, and src/cpp could be 1.1.4). **\[6.3.0] - 2025-11-21** **Added** * Added generics to NDI IP cores to enable/disable features * Agilex-7 encode example design **Changed** * Xilinx NDI IP cores modified to reduce BRAM usage * Xilinx kernel and boot loader build method : Zynq 7000 projects updated to Vivado 2024.2 **\[6.1.0] - 2024-11-22** **Added** * Virtual PTZ support to ndi\_encode application **Changed** * NDI Advanced SDK uses the `libndi_advanced` library now * SD card images updated with latest NDI library and example applications **\[6.1.0-rc1] - 2024-09-13** **Added** * Synchronize major version number with software SDK version * Encoder support for planar alpha * Support for new packed and semi-planar video formats * Support for 16-bit video (11-bits passed through SpeedHQ codec) * Support for 64-bit addressing in raw audio/video input and output logic **\[1.5.4] - 2024-01-24** **Added** * Example project for the Kria KV260 development board **Fixed** * A couple bugs in the clear-text FPGA logic **\[1.5.3] - 2023-08-25** **Changed** * Xilinx projects updated to Vivado 2022.1 * Zynq 7000 HDMI Rx Logic improved * SoCKit projects deprecated as boards are no longer available for purchase **\[1.5.0] - 2022-10-09** **Added** * Alpha support (interleaved and planar) added to NDI\_Dec : Example projects targeting the Arria-10 SoC Development Kit **Changed** * Updates for NDI v5.x **\[1.4.0] - 2020-03-25** **Added** : NDI Decode support **Changed** * Updates for NDI v4.5 : Xilinx & Petalinux projects updated to 2019.2 **\[1.3.0] - 2019-07-08** **Changed** * Updates for NDI v4.0 * Refactoring to support both encode and decode * Updates to device-tree layout and uio device names * Zybo uSD image modified to include all three examples (Encode, Encode-Lite, Decode) **\[1.2.1] - 2018-11-17** **Added** * Zybo-Z7-20-Lite example design (16-bit SDRAM interface with 2 encoder cores) **\[1.2.0] - 2018-10-03** **Added** * Auto-detect video format * Audio is now working **\[1.1.1] - 2018-09-25** **Changed** * Sub-project zip files now provided in expanded form * Restructured project directories **\[1.1.0] - 2018-08-31** **Added** * Support new hardware version register **Changed** * Updated NDI\_Demo hardware project files * Updated PetaLinux files **\[1.0.0] - 2018-07-13** **Added** * Initial version **Changelog Hints & Details** * [Changelog format](https://keepachangelog.com/en/1.0.0/) * [Semantic Versioning](https://semver.org/) ### FPGA Projects Changelog **\[6.3.0] - 2025-11-21** **Changed** * Add generics to enable/disable features in NDI IP cores * Add error bits to NDI IP cores indicating unsupported format requested * Reduced BRAM usage in Xilinx NDI IP cores (distributed RAM now used where appropraite) * Update Zybo and Arty projects to Vivado 2024.2 **Added** * Agilex-7 encoder project **\[6.1.0] - 2024-11-22** **Changed** * No changes from 6.1.0-rc1 **\[6.1.0-rc1] - 2024-09-13** **Changed** * Reset version numbering to align with software SDK * Memory simulation files now explicitly labeled as encoder or decoder specific * Many changes to decoder and encoder cores (see NDI 6.1 hardware changes for details) * Upgraded the message severity in Xilinx projects for missing memory initialization files (these are reported as errors now) * Rename output files to be consistent with top-level project name **Added** * Encoder support for planar alpha * Support for new packed and semi-planar video formats * Support for 16-bit video (11-bits passed through SpeedHQ codecs) * Add 6.1 decoder and encoder encrypted IP and memory initialization files to all example designs * Support for 64-bit addressing in raw audio/video input and output logic **Fixed** * NDI\_Enc change handling of VID\_BURST\_WIDTH generic so only legal Avalon burst lengths are generated. Previous logic used b"0000" to represent a 16 word burst when the correct value should be b"1\_0000", which becomes b"1111" when converted into an AXI arlen value * NDI\_Enc VID\_BURST\_WIDTH generic set to 5 for Zynq 7000 projects **\[1.5.4] - 2024-01-24** **Added** * Example project for the Kria KV260 development board **Fixed** * Local reset logic in Vid\_In, Vid\_Out, and Vid\_Track was ignoring rst * Bug in Avl\_Axi\_Wr could cause bus lockup under some conditions **\[1.5.3] - 2023-08-25** **Changed** * Xilinx projects updated to Vivado 2022.1 * Switch to performance optimized synthesis and implementation strategies to ease timing closure : Merged Hamsterworks HDMI handling with Digilent PHY * Update Xilinx encryption key to xilinxt\_2019\_02 **\[1.5.2] - 2023-01-12** **Changed** * Update SoCKit-Dec project to Quartus 22.1 **\[1.5.1] - 2022-09-19** **Added** * Initial example design for Arria-10 SoC Devkit * NDI\_Dec now supports writing planar alpha when PLANAR\_ALPHA generic is true * PLANAR\_ALPHA generic added to disable planar alpha logic if not needed **Fixed** * Inferred multiplier output register did not map to DSP block in Arria-10 **Changed** * Update generics for NDI\_Enc to support different read and write bus parameters * Update SoCKit-Dec project to Quartus 20.1.1 * Update SoCKit-Dec software files to SoC EDS 20.1 for U-Boot socfpga\_2021.10 **\[1.4.9] - 2022-07-12** **Fixed** * Updated cache and user bits in Avl\_Axi\_Wr.vhd to address cache coherency issues on the Zynq 7000 Encoder example causing corrupted bitstreams **\[1.4.8] - 2022-01-10** **Added** * Semantic versioning to NDI cores version register * wr\_alpha control bit to NDI\_Dec to enable writing alpha data **\[1.4.7] - 2021-11-24** **Added** * Disable bit to Vid\_Out.vhd * Support for variable counter widths in Vid\_Track.vhd **Fixed** * Encode\_x4 updated to properly merge audio input data with fewer than 4 cores (previous fix was incorrect) * Parallel audio left/right data swapped in Aud\_In.vhd **\[1.4.6] - 2021-11-04** **Added** : Missing dtsi files for Altera kernel **\[1.4.5] - 2021-03-30** **Fixed** * Encode\_x4 updated to properly merge audio input data with fewer than 4 cores * Update encode projects to read back zeros when accessing decoder addresses **Changed** * Routed FPGA SDRAM status signals to LEDs for SoCKit design **\[1.4.4] - 2021-03-02** **Added** * Initial version of Arty-Z7-20-Enc **\[1.4.3] - 2020-06-02** **Fixed** * Bug in Preview logic when set to divide by 2 in wide mode (720p on the ZCU104) * 4:2:2 to 4:4:4 conversion logic in DVI\_Tx.vhd **\[1.4.2] - 2020-05-20** **Fixed** * Problem with Altera specific Decode logic **\[1.4.1] - 2020-03-25** **Fixed** * Audio Output register address for ZCU104 Decode project **\[1.4.0] - 2020-03-20** **Changed** * Xilinx projects updated to Vivado 2019.2 * Intel (Altera) project updated to Quartus-Lite 19.1 * NDI Decode support **\[1.3.4] - 2020-03-17** **Added** * Initial version with audio output **Fixed** * Updated FIFO and command reset logic in Vid\_Out **\[1.3.3] - 2019-10-07** **Fixed** * Fixed quantized coefficient rounding in FPGA Encode logic so it matches the software **\[1.3.2] - 2019-09-20** **Changed** * NDI Decoder updated for Altera DSP blocks **\[1.3.1] - 2019-08-29** **Added** * ZCU104 decode reference design * Decode and output support for 4Kp60 4:2:0 video **Changed** * Update FPGA logic to improve timings * 4 Macroblock burst mode added to NDI\_Dec to improve SDRAM efficiency **\[1.3.0] - 2019-07-08** **Added** * Initial version with NDI Decode **Changed** * Added support for targeting all Encoder cores with a single write * Updated Altera licenses **\[1.2.2] - 2019-04-04** **Added** * Overview of Encoder core * NDI\_SoC+FPGA\_Encoder.pdf **Changed** * Updated block diagram and migrated it into Encoder overview pdf file **Fixed** * Update Avl\_Axi\_Wr.vhd to avoid bus lockup under rare conditions * Fix case mis-match with local.xdc file in Zybo-Z7-20-Lite project file **\[1.2.1] - 2018-11-17** **Added** * Zybo-Z7-20-Lite example design (16-bit SDRAM interface with 2 encoder cores) **Fixed** * Preview filter was not passing locked bit to output * Missing signal declaration in "Hamsterworks" HDMI audio logic * Encode\_x4 updated to properly support fewer than 4 cores **\[1.2.0] - 2018-09-30** **Added** * Audio support * Video tracking and auto-format detection **Changed** * Renamed ZCU104 project directory **\[1.1.2] - 2018-09-21** **Added** * Altera IP core and license file (example design coming soon!) * Hardware export directories * Compiled bit files **Fixed** * Slightly improved NDI encoder efficiency to improve performance at 4Kp60 when using a 200 MHz clock * Fix issue when switching between SD and HD modes * Fix wedging issue with specific memory latency and wait state patterns **\[1.1.1] - 2018-09-13** **Added** * HDMI embedded audio extraction * Digilent dvi2rgb added as an alternative video input **Fixed** * RGB to YCbCr color space conversion (B and R coefficients were swapped) **\[1.1.0] - 2018-08-31** **Added** * HDMI Input logic for Zybo platform, based on open-source code from Mike Field . Thanks Mike!!! * Version register including platform specifier * PS block design: axi\_gpio to interface to PL LEDs and push-button switches * PS block design: axi\_iic for audio codec I2C bus (Zybo) * Audio input logic added to Zybo project (not yet tested) * Details on compiling HDMI Rx code for the Cortex-R5 on the ZCU104 * Automated zip file package builds thanks to git archive (git ROCKS! :) ) **Fixed** * Critical warning regarding VIDEO\_CLK when building ZCU104 project * Issues caused by running on platforms with both 128-bit (ZCU104) and 64-bit (Zybo-Z7) interfaces to SDRAM. **Changed** * README.txt switched to markdown format and renamed to README.md * General code cleanup and removal of unnecessary files, comments, and deprecated code. * Added actual purging logic to VidIn, rather than just resetting the FIFO when VSYNC is active. **\[1.0.2] - 2018-08-07** **Changed** * Add Build Dependencies section to the README file indicating Digilent board files must be installed to properly build the example Zybo project and an HDMI license is required for the ZCU104. **Fixed** * Deprecated file "NDI\_Pkg.vhd" removed from Zybo-Z7-20 project file. **\[1.0.1] - 2018-07-26** **Added** * Changelog.md **Fixed** * Deprecated file "NDI\_Pkg.vhd" removed from zynqmp.NDI project file. **\[1.0.0] - 2018-07-13** **Added** * Initial version ### C++ Application Code Changelog **\[6.3.0] - 2025-11-21** **Added** * Support for new hardware error bits when requesting an unsupported format * Support for hardware configurations that were compiled without planar video or 16-bit format support **Changed** * The `NewTek_Reserved` and `NewTek_Video` reserved memory regions are looked up in the device tree by alias first and then, if absent, looked for directly in `/sys` **\[6.1.x] - 2024-12-31** **Added** * Support for playback of packed output video formats * 4:2:2 UYVY, YUYV, Y216, and UYVW formats * 4:2:0 420 and 420W formats * Support for luminance only playback of semi-planar 4:2:2 formats **Changed** * The `ndi_decode` appliation now supports strings instead of requiring numerical arguments to the `-o` option to indicate the output video format * Playback of 16-bit formats is truncated to 8-bit before being sent to the HDMI output interface **\[6.1.0] - 2024-11-22** **Added** * Virtual PTZ support to ndi\_encode application **Changed** * NDI Advanced SDK uses the `libndi_advanced` library now **\[6.1.0-rc1] - 2024-09-13** **Changed** * Reset version numbering to align with software SDK **Added** * Encoder support for planar alpha : Support for new packed and semi-planar video formats Support for 16-bit video (11-bits passed through SpeedHQ codec) * Additional decoder application features: * Burst vs. no-burst mode SDRAM transfers * New video capture class and command line options for capturing video frames * Output video format can be selected at run-time (default to 8-bit UYVY) **\[1.5.1] - 2023-01-13** **Added** * Support for Arria-10 SoC Developemnt Kit platform **Changed** * Disable CPU intensive protocols on lower-end platforms **\[1.5.0] - 2022-08-05** **Changed** * Updates for NDI 5.x * Remove frame copy functions in video\_compress.cpp * Pass scatter gather list and let NDI SDK perform the copy * Update examples with new NDI Vendor ID format **Fixed** * Changed pattern generator line stride to avoid issues in 4:2:0 mode **\[1.4.2] - 2022-07-12** **Fixed** * SSM2603 Line Input was not working **\[1.4.1] - 2020-03-27** **Changed** * n'Switch ZCU104 to I2S serial audio output format **\[1.4.0] - 2020-03-25** **Changed** * Updates for NDI v4.5 : NDI Decode support **\[1.3.3] - 2020-02-05** **Changed** * Switched to NDI SDK function to generate next Q value for video encoding * Updated single-character debug output so each character is unique **Fixed** * Addressed the various `FIXME` comments in the ndi\_encode application code **\[1.3.2] - 2020-01-07** **Added** * Support for SoCKit platform **\[1.3.1] - 2019-09-26** **Changed** * Code migrated to separate sub-directories for each target application * Makefile updates to better manage auto dependency generation **\[1.3.0] - 2019-07-08** **Changed** * Updates for NDI v4.0 * Refactoring to support both encode and decode **\[1.2.2] - 2018-11-17** **Added** * Support for changing reserved memory region size in device-tree * Support for fewer than 4 encoder cores **Fixed** * Unused variable warning when performing a release build **\[1.2.1] - 2018-10-10** **Added** : Support for changing frame rate in pattern generator mode **Changed** * Zybo audio codec setup migrated to ndi\_send application **Fixed** * Pattern Generator is working again * Pattern Generator 4K video mode is working * Video tracking thread was consuming excessive CPU cycles **\[1.2.0] - 2018-10-03** **Added** * Auto-detect video format * Audio is now working **\[1.1.1] - 2018-08-25** **Changed** * Sub-project zip files now provided in expanded form * Restructured project directories * ndi\_device renamed ndi\_send * Generate proper timestamps **Fixed** * Issue with potential use after free related to addition of copy thread **\[1.1.0] - 2018-08-31** **Added** * ndi\_reg utility * Support new hardware version register **Changed** * General cleanup and removal of deprecated/commented code * Pull details on raw video memory from device tree if available * Add copy thread to video path **\[1.0.0] - 2018-07-13** **Added** * Initial version ### Linux Kernel and Boot Loader Changelog **\[6.3.0] - 2025-11-21** **Added** * Agilex-7 kernel and boot-loader **Changed** * Updated Arty and Zybo targets to use Xilinx 2024.2 tools * Updated ZCU104 targets to use Xilinx 2022.1 tools * Makefile updated to build targets directly from Xilinx repositories instead of using PetaLinux * Removed Petalinux projects and Makefile logic **\[6.1.0] - 2024-11-22** **Changed** * No changes from 6.1.0-rc1 **\[6.1.0-rc1] - 2024-09-13** **Changed** * Reset version numbering to align with software SDK * Update Makefile to use new exported FPGA output file names **\[1.5.3] - 2023-08-25** **Changed** * Migrated all PetaLinux projects from 2019.2 to 2022.1 * Kernel version for Xilinx projects changed to 5.15.19 * All Zynq-7000 and UltraScale+ projects are automatically generated via make and bash scripts. * Petalinux project configuration and device tree modifications automatically incorporated **\[1.5.2] - 2023-01-12** **Added** * SoCKit updated to Quartus 22.1 **\[1.5.1] - 2022-09-22** **Added** * Initial support for Arria-10 SoC Development Kit * ndiname device-tree node for use as NDI machinename **Changed** * Removed deprecated Petalinux 2018.1 projects * Move reserved memory regions in Zybo-Z7-20-Lite device-tree **\[1.4.2] - 2021-03-08** **Added** * Initial support for Arty-Z7-20 **\[1.4.1] - 2020-03-27** **Fixed** * R5 remoteproc device-tree entries for ZCU104-Dec project were broken **Added** * Added prebuilt boot files required to generate uSD images **\[1.4.0] - 2020-03-25** **Changed** * Updates for NDI v4.5 : Petalniux projects updated to 2019.2 : NDI Decode support **\[1.3.3] - 2020-03-08** **Added** * Petalinux 2019.2 project for ZCU104 ndi\_encode **\[1.3.2] - 2020-01-07** **Changed** * Modified Zybo boot arguments to support new partition layout * Updated pre-compiled files with latest FPGA bit files **Fixed** * Added missing pre-comiled U-Boot files for ZCU104 projects **\[1.3.1] - 2019-07-11** **Fixed** * Updated pre-compiled files to allow update of the various FPGA bit files (NDI Encode, Encode-Lite, and Decode) without rebuilding from scratch **\[1.3.0] - 2019-07-01** **Added** * Updates for NDI v4.0 **Changed** * Updated system-user.dtsi files to support NDI Decode * Updated pre-compiled files **\[1.2.1] - 2018-11-15** **Fixed** * Missing dash in `--get-hw-description` petalinux command **\[1.2.0] - 2018-09-30** **Added** * Added pre-compiled boot files, allowing update of the FPGA bit file without recompiling PetaLinux from scratch : Added tracking logic to system-user.dtsi **Changed** * Tally LEDs default to on at boot instead of the heartbeat trigger : Unused LEDs set to cpu and uSD trigger **\[1.1.1] - 2018-09-24** **Changed** * Update boot.sh scripts to reference bit file in `src/fpga/` directories **Removed** * FPGA bit files (migrated to `src/fpga/`) : Hardware export directories (migrated to `src/fpga/`) **\[1.1.0] - 2018-09-05** **Added** * Hardware export sdk directories from Vivado **Changed** * Projects updated with latest FPGA hardware export : Device-tree entries added for tally LEDs **\[1.0.0] - 2018-08-17** **Added** * Initial version ### uSD Image Builder Changelog **\[6.3.0] - 2025-11-21** **Changed** * Switched root filesystem from Debian 12 (bookworm) to Debian 13 (trixie) * Update prebuilt tarballs with current NDI library and applications * Create zip file after generating img.xz, bmap, and md5 files * Output product location can now be specified with `LOCAL_TMP` * Update Xilinx configurations with new locations for kernel and bootloader **Added** * Agilex-7 configuration **\[6.1.0] - 2024-11-22** **Changed** * Update prebuilt tarballs with current NDI library and applications **\[6.1.0-rc1] - 2024-09-13** **Changed** * Reset version numbering to align with software SDK : Update prebuilt tarballs with current NDI library and applications **\[1.5.3] - 2023-08-25** **Changed** * Switched root filesystem from Debian 11 (bullseye) to Debian 12 (bookworm) * Build updates for Petalinux 2022.1 * Using extlinux.conf instead of boot.scr due to changes with newer versions of the Xilinx tools * Debootstrap now requires transparent emulation via QEMU **\[1.5.1] - 2022-09-24** **Added** * Image configuration for Arria-10 SoC Development Kit **Changed** * Update from Debian stretch to Bullseye * Altera boot files updated to match current U-Boot generated files **\[1.4.0] - 2020-03-25** **Added** * Updates for NDI v4.5 : Composite uSD image supporting both Xilnix Digilent Zybo-Z7 and Intel/Altera Terasic SoCKit boards using the same uSD image * NDI Decode support **\[1.3.1] - 2020-01-07** **Changed** * Change partition layout for armhf configurations to allow dual booting of Zybo-Z7-20 and SoCKit boards with the same uSD image * Switch back to upstream head for libuio source code **\[1.3.0] - 2019-07-07** **Added** * Updates for NDI v4.0 **Changed** * Allow for multiple boot filesets in uSD image generation * Switch libuio repository used to build from source * Upstream broke uio nodes with no map entry **\[1.1.1] - 2018-09-25** **Added** * Resize root partition on first boot **Changed** * Updated for new directory structure **\[1.1.0] - 2018-09-09** **Added** * CHANGELOG.md : build.sh script to do (mostly) everything to make an image : update.tgz.sh **Changed** * Switched to using \*.conf files for image details * Factored general setup into common.sh : Lots of code cleanup **\[1.0.0] - 2018-07-13** **Added** * Initial version --- # Agent Instructions: Querying This Documentation If you need additional information that is not directly available in this page, you can query the documentation dynamically by asking a question. Perform an HTTP GET request on the current page URL with the `ask` query parameter: ``` GET https://docs.ndi.video/all/developing-with-ndi/advanced-sdk/ndi-advanced-sdk-fpga-example-reference-design/ndi-advanced-sdk-fpga-ip/changelog.md?ask= ``` The question should be specific, self-contained, and written in natural language. The response will contain a direct answer to the question and relevant excerpts and sources from the documentation. Use this mechanism when the answer is not explicitly present in the current page, you need clarification or additional context, or you want to retrieve related documentation sections.