# NDI Encoding Support Matrix

> ## SpeedHQ

<table data-full-width="true"><thead><tr><th>CODEC</th><th>SpeedHQ0  4:2:0 8bit</th><th>SpeedHQ2  4:2:2 8bit</th><th>SpeedHQ2  4:2:2 10bit</th><th>SpeedHQ7 4:2:2:4 8bit</th><th>SpeedHQ7 4:2:2:4 10bit</th></tr></thead><tbody><tr><td><strong>FPGA Encoding²</strong></td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td></tr><tr><td><strong>FPGA Decoding</strong></td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td></tr><tr><td><strong>Hardware Video Encoder (VCU)</strong></td><td>NO</td><td>NO</td><td>NO</td><td>NO</td><td>NO</td></tr><tr><td><strong>Hardware Video Decoder</strong></td><td>NO</td><td>NO</td><td>NO</td><td>NO</td><td>NO</td></tr><tr><td><strong>Software Encoding</strong></td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td></tr><tr><td><strong>Software Decoding</strong></td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td></tr></tbody></table>

***

> ## HX

<table data-full-width="true"><thead><tr><th>CODEC</th><th width="166.39996337890625">HX (v1) H.264 4:2:0 8bit</th><th width="144.79998779296875">HX (v2) H.264 4:2:0 8bit</th><th>HX (v2) H.265 4:2:0 8bit</th><th>HX (v2) H.265 4:2:0 10bit</th><th>HX3 H.264  4:2:0 8bit</th><th>HX3 H.265  4:2:0 8bit</th><th>HX3 H.265  4:2:0 10bit</th></tr></thead><tbody><tr><td><strong>FPGA Encoding²</strong></td><td>NO</td><td>NO</td><td>NO</td><td>NO</td><td>NO</td><td>NO</td><td>NO</td></tr><tr><td><strong>FPGA Decoding</strong></td><td>NO</td><td>NO</td><td>NO</td><td>NO</td><td>NO</td><td>NO</td><td>NO</td></tr><tr><td><strong>Hardware Video Encoder (VCU)</strong></td><td>NO</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td></tr><tr><td><strong>Hardware Video Decoder</strong></td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td></tr><tr><td><strong>Software Encoding</strong></td><td>NO</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td></tr><tr><td><strong>Software Decoding</strong></td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td><td>YES</td></tr></tbody></table>

{% hint style="info" %}
The FPGA implementations include a SpeedHQ codec in the FPGA fabric for speed, but can *also* use the same software codec as the regular SDK. Typically, the ARM CPU cores on the FPGA+SoC devices are slow enough that decoding video in software is impractical, but this is gradually changing as everything gets faster. (Charles Steinkuehler)
{% endhint %}


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