# Changelog

## Changelog

### \[6.1.0] - 2024-11-22

No changes from 6.1.0-rc1

### \[6.1.0-rc1] - 2024-09-13

#### Changed

* Reset version numbering to align with software SDK
* Memory simulation files now explicitly labeled as encoder or decoder specific
* Many changes to decoder and encoder cores (see NDI 6.1 hardware changes for details)
* Upgraded the message severity in Xilinx projects for missing memory initialization files (these are reported as errors now)
* Rename output files to be consistent with top-level project name

#### Added

* Encoder support for planar alpha
* Support for new packed and semi-planar video formats
* Support for 16-bit video (11-bits passed through SpeedHQ codecs)
* Add 6.1 decoder and encoder encrypted IP and memory initialization files to all example designs
* Support for 64-bit addressing in raw audio/video input and output logic

#### Fixed

* NDI\_Enc change handling of VID\_BURST\_WIDTH generic so only legal Avalon burst lengths are generated. Previous logic used b"0000" to represent a 16 word burst when the correct value should be b"1\_0000", which becomes b"1111" when converted into an AXI arlen value
* NDI\_Enc VID\_BURST\_WIDTH generic set to 5 for Zynq 7000 projects

### \[1.5.4] - 2024-01-24

#### Added

* Example project for the Kria KV260 development board

#### Fixed

* Local reset logic in Vid\_In, Vid\_Out, and Vid\_Track was ignoring rst
* Bug in Avl\_Axi\_Wr could cause bus lockup under some conditions

### \[1.5.3] - 2023-08-25

#### Changed

* Xilinx projects updated to Vivado 2022.1
* Switch to performance optimized synthesis and implementation strategies to ease timing closure
* Merged Hamsterworks HDMI handling with Digilent PHY
* Update Xilinx encryption key to xilinxt\_2019\_02

### \[1.5.2] - 2023-01-12

#### Changed

* Update SoCKit-Dec project to Quartus 22.1

### \[1.5.1] - 2022-09-19

#### Added

* Initial example design for Arria-10 SoC Devkit
* NDI\_Dec now supports writing planar alpha when PLANAR\_ALPHA generic is true
* PLANAR\_ALPHA generic added to disable planar alpha logic if not needed

#### Fixed

* Inferred multiplier output register did not map to DSP block in Arria-10

#### Changed

* Update generics for NDI\_Enc to support different read and write bus parameters
* Update SoCKit-Dec project to Quartus 20.1.1
* Update SoCKit-Dec software files to SoC EDS 20.1 for U-Boot socfpga\_2021.10

### \[1.4.9] - 2022-07-12

#### Fixed

* Updated cache and user bits in Avl\_Axi\_Wr.vhd to address cache coherency issues on the Zynq 7000 Encoder example causing corrupted bitstreams

### \[1.4.8] - 2022-01-10

#### Added

* Semantic versioning to NDI cores version register
* wr\_alpha control bit to NDI\_Dec to enable writing alpha data

### \[1.4.7] - 2021-11-24

#### Added

* Disable bit to Vid\_Out.vhd
* Support for variable counter widths in Vid\_Track.vhd

#### Fixed

* Encode\_x4 updated to properly merge audio input data with fewer than 4 cores (previous fix was incorrect)
* Parallel audio left/right data swapped in Aud\_In.vhd

### \[1.4.6] - 2021-11-04

#### Added

* Missing dtsi files for Altera kernel

### \[1.4.5] - 2021-03-30

#### Fixed

* Encode\_x4 updated to properly merge audio input data with fewer than 4 cores
* Update encode projects to read back zeros when accessing decoder addresses

#### Changed

* Routed FPGA SDRAM status signals to LEDs for SoCKit design

### \[1.4.4] - 2021-03-02

#### Added

* Initial version of Arty-Z7-20-Enc

### \[1.4.3] - 2020-06-02

#### Fixed

* Bug in Preview logic when set to divide by 2 in wide mode (720p on the ZCU104)
* 4:2:2 to 4:4:4 conversion logic in DVI\_Tx.vhd

### \[1.4.2] - 2020-05-20

#### Fixed

* Problem with Altera specific Decode logic

### \[1.4.1] - 2020-03-25

#### Fixed

* Audio Output register address for ZCU104 Decode project

### \[1.4.0] - 2020-03-20

#### Changed

* Xilinx projects updated to Vivado 2019.2
* Intel (Altera) project updated to Quartus-Lite 19.1
* NDI Decode support

### \[1.3.4] - 2020-03-17

#### Added

* Initial version with audio output

#### Fixed

* Updated FIFO and command reset logic in Vid\_Out

### \[1.3.3] - 2019-10-07

#### Fixed

* Fixed quantized coefficient rounding in FPGA Encode logic so it matches the software

### \[1.3.2] - 2019-09-20

#### Changed

* NDI Decoder updated for Altera DSP blocks

### \[1.3.1] - 2019-08-29

#### Added

* ZCU104 decode reference design
* Decode and output support for 4Kp60 4:2:0 video

#### Changed

* Update FPGA logic to improve timings
* 4 Macroblock burst mode added to NDI\_Dec to improve SDRAM efficiency

### \[1.3.0] - 2019-07-08

#### Added

* Initial version with NDI Decode

#### Changed

* Added support for targeting all Encoder cores with a single write
* Updated Altera licenses

### \[1.2.2] - 2019-04-04

#### Added

* Overview of Encoder core: NDI\_SoC+FPGA\_Encoder.pdf

#### Changed

* Updated block diagram and migrated it into Encoder overview pdf file

#### Fixed

* Update Avl\_Axi\_Wr.vhd to avoid bus lockup under rare conditions
* Fix case mis-match with local.xdc file in Zybo-Z7-20-Lite project file

### \[1.2.1] - 2018-11-17

#### Added

* Zybo-Z7-20-Lite example design (16-bit SDRAM interface with 2 encoder cores)

#### Fixed

* Preview filter was not passing locked bit to output
* Missing signal declaration in "Hamsterworks" HDMI audio logic
* Encode\_x4 updated to properly support fewer than 4 cores

### \[1.2.0] - 2018-09-30

#### Added

* Audio support
* Video tracking and auto-format detection

#### Changed

* Renamed ZCU104 project directory

### \[1.1.2] - 2018-09-21

#### Added

* Altera IP core and license file (example design coming soon!)
* Hardware export directories
* Compiled bit files

#### Fixed

* Slightly improved NDI encoder efficiency to improve performance at 4Kp60 when using a 200 MHz clock
* Fix issue when switching between SD and HD modes
* Fix wedging issue with specific memory latency and wait state patterns

### \[1.1.1] - 2018-09-13

#### Added

* HDMI embedded audio extraction
* Digilent dvi2rgb added as an alternative video input

#### Fixed

* RGB to YCbCr color space conversion (B and R coefficients were swapped)

### \[1.1.0] - 2018-08-31

#### Added

* HDMI Input logic for Zybo platform, based on open-source code from Mike Field <hamster@snap.net.nz>. Thanks Mike!!!
* Version register including platform specifier
* PS block design: axi\_gpio to interface to PL LEDs and push-button switches
* PS block design: axi\_iic for audio codec I2C bus (Zybo)
* Audio input logic added to Zybo project (not yet tested)
* Details on compiling HDMI Rx code for the Cortex-R5 on the ZCU104
* Automated zip file package builds thanks to git archive (git ROCKS! :) )

#### Fixed

* Critical warning regarding VIDEO\_CLK when building ZCU104 project
* Issues caused by running on platforms with both 128-bit (ZCU104) and 64-bit (Zybo-Z7) interfaces to SDRAM.

#### Changed

* README.txt switched to markdown format and renamed to README.md
* General code cleanup and removal of unnecessary files, comments, and deprecated code.
* Added actual purging logic to VidIn, rather than just resetting the FIFO when VSYNC is active.

### \[1.0.2] - 2018-08-07

#### Changed

* Add Build Dependencies section to the README file indicating Digilent board files must be installed to properly build the example Zybo project and an HDMI license is required for the ZCU104.

#### Fixed

* Deprecated file "NDI\_Pkg.vhd" removed from Zybo-Z7-20 project file.

### \[1.0.1] - 2018-07-26

#### Added

* Changelog.md

#### Fixed

* Deprecated file "NDI\_Pkg.vhd" removed from zynqmp.NDI project file.

### \[1.0.0] - 2018-07-13

* Initial version

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